1. Field of the Invention
The invention relates to a semiconductor integrated circuit (decoder circuit) suitable for speed-up in operation and lower power consumption, and a semiconductor memory using the same.
2. Description of the Prior Art
FIG. 12(a) shows a decoder circuit used in a semiconductor memory by way of an example of a conventional decoder circuit. The decoder circuit described above is disclosed in Japanese Patent Laid-open No. Hei10-150358. In FIG. 12(a), reference numerals XB0, XB1 indicate address buffers, A0, A1 indicate address inputs, N1 to N4 indicate inverters, VB0 to/VB1 indicate buffer outputs (or buffer output lines), XDE0 to XDE3 indicate decoders, output 0 to output 3 indicate decoder outputs (or decoder output lines) Φ1 indicates an address buffer control signal, and Φ2 indicates a decoder control signal. In the figure, a circuit configuration on the scale of four decoder output lines is shown by way of example. With the decoder circuit, a source-coupled-logic circuit (referred to hereinafter as a SCL circuit) is used for the address buffers and the decoders, and the decoder circuit has the following features. Firstly, buffer output signals (OR, NOR) have nearly equal delay time, respectively, and are suitable as inputs to the decoders. Secondly, even if the number of inputs to the decoders is large, the number of stacked stages of n-type transistors (MN1, MN2) for pull-down of an output section will not increase to more than two stages because the input transistors are connected in parallel in configuration. Hence, the decoder circuit is regarded a high-speed decoder circuit.
As shown in a timing chart of FIG. 12(b), however, a timing margin ts2 is required between the buffer outputs VB0 to/VB1 and the decoder control signal Φ2. The timing margin ts2 becomes a factor for blocking furtherance in speed-up of operation.
It is therefore an object of the invention to develop a circuit configuration wherein the decoder control signal Φ2 is unnecessary, thereby implementing speed-up in the operation of the decoder circuit.